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Saturday, August 8, 2020 | History

2 edition of An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple samples per second in 40nm CMOS found in the catalog.

An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple samples per second in 40nm CMOS

An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple samples per second in 40nm CMOS

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Published by Association of Scientists, Developers and Faculties in Chennai, India .
Written in English


About the Edition

A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. To implement power efficient and high performance analog-to-digital converters the designers are urged to design an optimized dual tail comparator. In this paper, It is shown that in the proposed dual tail comparator both the power and delay time is significantly reduced.

ID Numbers
Open LibraryOL25927109M
ISBN 10978-81-929866-5-4


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An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple samples per second in 40nm CMOS Download PDF EPUB FB2